Microfiche Appendix A, which is part of the present disclosure, is an appendix consisting 4 sheets of microfiche having 195 frames. Microfiche Appendix A lists source code of a computer program and related data of an illustrative embodiment of the present invention for use in an industry standard Sun Solaris Machine(trademark). Appendices B and C which are part of the present disclosure, are a pseudo code listing and a Verilog listing, respectively.
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1. Field of the Invention
This invention relates to pipeline and cycle modeling for software simulation techniques of hardware modules and software-software cross-simulation and software-hardware co-simulations of hardware modules.
2. Description of Related Art
Software simulation of electronic components and systems has become an important tool for designers. Simulation of a design is the execution of an algorithm that models the behavior of the actual design. Simulation provides the ability to analyze and verify a design without actually constructing the design and has many benefits in the design process. Simulation techniques have also been used for a variety of applications including simulation of digital signal processors (DSPs). Such simulations have included pipeline modeling as well as clock cycle modeling. However, such simulations are limited in many ways.
In the case of pipeline modeling for processors, conventional simulations either did not model the pipelines or a backward history method was employed. In a conventional simulation that did not model the pipelines, every instruction was considered to be executed during one instruction cycle, i.e., every instruction was fetched, decoded, and executed during a single cycle. However, because a pipelined processor does not fetch, decode, and execute each instruction during one instruction cycle, this method is not cycle accurate.
Using the backward history method, the pipeline state was stored in a memory for a predetermined number of cycles backwards, i.e., a number of previously executed states were stored for use in decision making during a current cycle. This was an extremely cumbersome and complicated method which requires decision tree evaluations to decide what should be executed during the current cycle.
In the case of simulation of hardware modules, many multi-stage software techniques have existed for modeling of clock cycles within the hardware; however, those techniques have been limited in the accuracy of clock cycle correlation between different modules and/or simulations.
Testing and verification of hardware modules and microprocessors have been performed with software simulation modules in place of the actual hardware. Unfortunately, it is difficult for clock cycle modeling to support simultaneous cycle accurate hardware modeling, software/hardware co-simulation, and software/software cross-simulation.
In accordance with the invention, a method of modeling a processor with software is described. One aspect of modeling involves simulating a processor pipeline which has a plurality of stages, e.g., a three-stage pipeline. This involves fetching an instruction, which is then subdivided into several individual actions. These actions include a decode action and an execution action. Upon subdividing the instruction, these actions are then stored in various queues. For instance, for a current cycle, N, a decode action could be inserted into the following queue for cycle, N+1, and an execution action could be inserted into the next following queue for cycle, N+2. Once these actions are inserted into their respective queues, the current cycle is evaluated and the results stored. It should beunderstood that there may be more than one action or no actions per each storage.
This method of pipeline modeling can be applied to any multi-stage pipeline with any number of stages and provides a way of processing forward-looking queues without having to utilize decisions or decision tree evaluations.
Aside from pipeline modeling, another aspect of processor modeling is clock cycle simulation. Clock cycle simulation involves modeling of clock cycles in a hardware module with a software model. Each simulated clock cycle involves several individual stages: Start, Execute, and End. During the start stage, output pin values for the module are calculated from a state of the module being simulated. A combinatorial function of module outputs can be calculated between start and execution stages. These calculated functions may be used as inputs to the modules in execution stage. Afterwards, during the execute stage, input pin values are received by the model and the next module state is calculated based upon the current module state and the input pin values. Finally, during the last stage, i.e., the end stage, the internal module state is updated; the internal module state is defined as a set of the module""s internal register and memory values.
This method of separating stages into a start, execute, and end stage enables not only software simulation of hardware modules with cycle accuracy, but also software-to-software cross-simulation between software models. Also, software-to-hardware co-simulation between a software model and a hardware module is possible because of the accuracy of the cycle modeling between actual modules and simulated modules.
Both the pipeline modeling and the clock cycle modeling used together represent a complete and efficient platform for development of software simulators of hardware modules. They also represent an efficient method of simulation which is able to be implemented in a wide variety of designs and in a wide variety of computer languages.